Semiconductor memories having memory cells that store logics according to resistance values, which have been known in the art, and include: a spin transfer Magnetic Random Access Memory (MRAM), a Phase change Random Access Memory (PRAM), a Resistive Random Access Memory (ReRAM), and a current induced magnetic field Magnetic Random Access Memory (MRAM). In this kind of semiconductor memory, current passing through a memory cell in readout operation varies depending on a resistance value. Thus, the logic held in the memory cell is readable by detecting a current value or voltage.
As a memory cell of this kind of the semiconductor memory, for example, a memory cell having: a pair of tunnel magneto resistive (TMR) elements, in which logics opposite to each other are written; and a transistor having a gate connected to a connection node of the TMR element and a source connected to a data line has been proposed. In read operation, the transistor is turned on or off due to a current represented on a connection node depending on the resistance value of the TMR element to determine logics held in the memory cell.
An example of a related art reference includes the following document:
Japanese Laid-open Patent Publication No. 2006-526907 (corresponds to US Publication No. 2007/0164781).
To read the logic of data held in the memory cell in read operation, during the read operation, the voltage of a connection node should be generated with high accuracy depending on the logic held in the memory cell and the transistor should be turned on or off in an effective manner.